The present invention generally relates to a semiconductor memory, and particularly relates to the configuration and production method of a dynamic RAM.
Semiconductor memory cells with a trench capacitor structure have become widely used as the density of the semiconductor memories has increased. FIGS. 1 and 2 show the structure of a typical memory cell. This structure is known as an IVEC (isolation-merged vertical capacitor) cell as reported by Nakajima et al. in IEDM, Lecture No. 9.4, 1984. Cells 1 each enclosed by an oxide film 2 are formed in a silicon substrate 9. A gate 5 and a contact 6 are formed on the upper portion of the cell 1, a contact 4 is provided between the cell 1 and a polysilicon node 3, an insulating film 11 is formed on the surface of the polysilicon node 3, and then a polysilicon plate 7 is formed.
The structure of such a memory cell, however, has the following problems.
That is, since the memory cell has a so-called one-cell one-contact structure, the contact forming portion is large as compared with the case of a so-called two-cell one-contact structure, and the one-cell one-contact structure becomes a large obstruction in making the structure fine. In order to realize the two-cell one-contact structure, however, the semiconductor memory becomes complicated to make it very difficult to put the structure into practical use.
As for a method of producing a dynamic RAM, on the other hand, there has been a problem in that a dynamic RAM has a complicated shape because of its trench capacitor and the process of production thereof is so difficult as to reduce the manufacturing yield. Particularly, there is a serious difficulty in the process of connecting an electrode formed in a trench to a transfer gate.
Two conventionally reported examples of the producing method will be specifically described hereunder.
As one of those examples, MINT reported by D. Kenney et al. of IBM Corp. in 1988 Symposium on VLSI Technology will be described with reference to a perspective view of FIG. 3.
A polysilicon electrode 32 provided in a trench is connected through a strap 37 to a source region 33 of a transfer gate 34. The strap 37 is formed by silicifying titanium by using a self-aligning method.
As another example, the connection method reported in T. Kaga et al.: "A 5.4 .mu.m.sup.2 Sheath-Plate-Capacitor DRAM Cell with Self-Aligned Storage-Node Insulation", 19th Conference on Solid State Devices and Materials, Tokyo, 1987, pp. 15-18 will be described with reference to FIG. 4. According to this method, a connection portion 48 is selectively provided by burying polysilicon 49 by utilizing the presence of a difference in height between a connection portion of the trench and a non-connection portion. That is, the connection portion 48 is formed by diffusion of phosphorus from the polysilicon 49 into a silicon substrate 41.
In the foregoing conventional producing methods, however, the following problems exist. In the method of FIG. 3, titanium is silicified to form a connection between the polysilicon electrode 32 and the source region 33 by using the strap 37. The silicification of titanium in an ultra-LSI process has a difficult problem in putting the method into practical use, so that the method cannot be used at all in producing memories of LSI circuits. In the connection method of FIG. 4, the process of connection is very difficult to carry out, resulting in problems with respect to manufacturing yields.